Synchronization can involve latching a signal from a first clock domain to a second clock domain. In certain applications, the second clock domain is not aligned to the first clock domain. As a result, the signal in the first clock domain can change state during a setup or a hold time, which can result in the latched signal in the second clock domain having a metastable condition. A metastable signal is neither a stable logic 0 nor a stable logic 1, and can thus potentially cause a critical system failure.
A common equation for a synchronizer can be expressed as:MTBF=e(Tr/τ)/(2*fDATA*fCLOCK*TO)  Equation 1                Where:                    MTBF=Mean Time Between Failures            Tr=Metastability Resolving Time            τ=Resolution Rate            2*fDATA=Incoming Edge Rate            fCLOCK=Clock Frequency            TO=Metastability ApertureThe Metastability Resolving Time Tr can be a time that is associated with the time available for a metastable condition to resolve itself. It can generally be expressed as a clock period minus a setup delay and propagation delays of any intermediate logic. In addition, for a multiple stage synchronizer, Tr can be the total resolving time of all the stages. The Metastability Aperture TO is a constant related to a width of time window during which an input transition will cause a metastability event. The Resolution Rate τ and the Metastability Aperture TO can both be experimentally measured.                        
Delay can be added in synchronization applications to prevent a race condition, in which an output of a first latching device from racing to a subsequent latching device. Despite the effectiveness of a pulse latch in a high frequency application due to its simplicity, a race condition can be especially severe in a pulsed latch based on process variations related to pulse width. A race condition can be mitigated by introducing a delay into the latching of a subsequent stage. However, in high frequency applications, the delay can consume a significant portion of the clock cycle, leaving less time to resolve the metastable condition (i.e., Metastable Resolving Time Tr). Due to the exponential relationship between the Metastable Resolving Time Tr and the MTBF, a reduction of Tr can severely increase a rate of failure.